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s 6b 0 723 132 seg / 65 com driver & controller for stn lcd june. 2000. ver . 0.9 prepared by: kyu-tae , lim k yutae @samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 2 S6B0723 specification revision history version content date 0.0 initial v ersion 1998 0.1 1. v dd level changed(1.8v ~ 3.6v ? 2.4v ~ 5.5v) 2. power save mode changed (compound instruction) 3. oscillator on command deleted 4. vref voltage changed (1.4v ? 2.1 v) 5. internal resistor (ra / rb) ratio changed 6. n-line inversion deleted mar.1999 0.2 1. pad name change d (vss ? test4) mar.1999 0.3 1. eq2 . changed (page 32) mar.1999 0.4 1. figure 10. figure 11. changed mar.1999 0.5 1. set static indicator register changed (page 46) apr.1999 0.6 1. modify following sections introduction, features, pad configuration, pin description, power supply circuits, reference circuit examples, dc/ac characteristics, connection between S6B0723 and lcd panel apr.1999 0.7 1. S6B0723 application circuit is changed(page 65~67) aug.1999 0.8 1. operating vdd range is changed oct .1999 0.9 1. read timing is changed(figure 5) jun .2000
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 features ................................ ................................ ................................ ................................ .......................... 1 block diagram ................................ ................................ ................................ ................................ ............... 3 pad configuration ................................ ................................ ................................ ................................ ....... 4 pad center coordinates ................................ ................................ ................................ ............................ 5 pin description ................................ ................................ ................................ ................................ .............. 8 power supply ................................ ................................ ................................ ................................ .......... 8 lcd driver supply ................................ ................................ ................................ ................................ .. 8 system control ................................ ................................ ................................ ................................ ..... 9 microprocessor interface ................................ ................................ ................................ ............. 11 lcd driver outputs ................................ ................................ ................................ ............................. 13 functional description ................................ ................................ ................................ ............................ 14 microprocessor interface ................................ ................................ ................................ ............. 14 display data ram (ddram) ................................ ................................ ................................ .................. 18 lcd display circuits ................................ ................................ ................................ ............................ 21 lcd driver circuits ................................ ................................ ................................ ............................. 24 power supply circuits ................................ ................................ ................................ ...................... 25 reference circuit examples ................................ ................................ ................................ ........... 32 reset circuit ................................ ................................ ................................ ................................ ......... 34 instruction description ................................ ................................ ................................ ........................... 35 specifications ................................ ................................ ................................ ................................ .............. 50 absolute maximum ratings ................................ ................................ ................................ ............... 50 dc characteristics ................................ ................................ ................................ ............................. 51 ac characteristics ................................ ................................ ................................ ............................. 54 reference applications ................................ ................................ ................................ ........................... 58 microprocessor interface ................................ ................................ ................................ ............. 58 connections between S6B0723 and lcd panel ................................ ................................ ............ 59 S6B0723 application circuit (6800 / 8080 / serial) ................................ ................................ ......... 65 tcp pin layout (sample) ................................ ................................ ................................ ...................... 68
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 1 introduction the S6B0723 is a single-chip driver & controller lsi for graphic dot-matrix liquid crystal display systems. this chip can be connected directly to a microprocessor, accepts serial or 8-bit parallel display data from the microprocessor, stores the display data in an on-chip display data ram of 65 x 1 32 bits and generates a liquid crystal display drive signal independent of the microprocessor . it provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. it contains 6 5 common driver circuits and 1 32 segment driver circuits, so that a single chip can drive a 65 x 132 dot display. and the capacity of the display can be increased through the use of master/slave multi-chip structures. this chip is able to minimize power consumption because it performs display data ram read/write operation with no external operation clock . in addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high-accuracy voltage regulator circuit, low power consumption voltage divider resistors and op-amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems . features display driver output circuits - 6 5 common outputs / 1 32 segment outputs on-chip display data ram - capacity: 65 x 1 32 = 8 , 58 0 bits - ram bit data ? 1 ? : a dot of display is illuminated. - ram bit data ? 0 ? : a dot of display is not illuminated. applicable duty ratios d uty ratio applicable lcd bias maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 1 32 1/55 1/6 or 1/8 55 132 1/49 1/6 or 1/8 49 132 1/33 1/5 or 1/6 33 132 microprocessor interface - high-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series - serial interface (only write operation) available various function set - display on / off, set initial display line, set page address, set column address, read status, write / read d isplay data, select segment driver output, reverse display on / off, entire display on / off, select lcd bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for v0 voltage regulation, electronic volume, set static indicator state. - h/w and s/w reset available - static drive circuit equipped internally for indicators with 4 flashing modes
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 2 built-in a nalog c ircuit - on-chip oscillator circuit for display clock (external clock can also be used) - high performance v oltage converter ( with booster ratios of x2 , x3, x4 and x5 , where the step-up reference voltage can be used externally ) - high accuracy voltage regulator (temperature coefficient: -0.05%/ c or external input ) - electronic contrast control function (64 steps) - vref = 2.1v 3% (v0 voltage adjustment voltage) - high performance v oltage follower (v1 to v4 voltage divider resistors and op-amp for increasing drive capacity) operating voltage range - supply voltage (v dd ): 2.4 to 3.6 v - lcd driving voltage (v lcd = v0 - v ss ): 4. 5 to 1 5 .0v low power consumption - operating power: 40 m a t yp ical (c onditions: v dd = 3v, x 4 boosting (vci = v dd ), v0 = 11v, internal power supply on , display o ff and normal mode is selected ) - standby power: 10 m a max imum (d uring power save[s tandby] mode) operating temperatures - wide range of operating temperatures : -40 to 85 c cmos process package type - tcp
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 3 block diagram ms cl m frs fr disp duty0 duty1 v dd v0 v1 v2 v3 v4 v ss hpmb v0 vr intrs ref vext vout c1- c1+ c2- c2+ c3 + c 4+ vci v / c circuit v / r circuit v / f circuit 33 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line address circuit page address circuit display data ram 65 x 1 32 = 8 , 58 0 bits display data control circuit display timing generator circuit common output controller circuit test1 test2 test3 db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) c68 resetb p s rw_wrb e_rd r s c s2 cs1b coms com63 : com32 seg131 seg130 seg129 : : seg2 seg1 seg0 com31 : com0 coms oscillator 1 32 segment driver circuits 33 common driver circuits i/o buffer status register instruction register cls figure 1 . block diagram
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 4 pad configuration eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 1 37 2 96 1 36 2 97 126 307 125 1 s 6b 07 23 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee figure 2 . S6B0723 chip configuration table 1 . S6B0723 pad dimensions size item pad no. x y unit chip size - 8850 198 0 1 51 to 282 52 2 to 21, 105 to 124 138 to 150, 283 to 295 55 22 to 104 70 150 to 151, 282 to 283 75 1 to 2, 124 to 125 137 to 138, 295 to 296 80 126 to 136, 297 to 307 150 pad pitch 2 1 to 22, 104 to 105 226 1 , 125, 137, 296 62 70 2 to 21, 105 to 124 138 to 150, 283 to 295 34 70 1 51 to 2 82 34 70 2 2 to 10 4 52 70 bumped pad size ( b ottom ) 126 to 136, 297 to 307 38 70 bumped pad height a ll pad 1 4 ( typ.) m m cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (+4078.7, - 397.2) 30 m m 30 m m 30 m m (+4078.25, +186.95) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-4134.2, +451.95) (+4144.25, +436.95) 42 m m 108 m m
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 5 pad center coordinates table 2 . p ad center coordinates [unit: m m] pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dummy com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms frs fr test1 test2 test3 m cl disp test4 vss cs1b cs2 vdd resetb rs vss rw_wrb e_rdb vdd db0 db1 db2 db3 db4 db5 db6 db7 vss vdd -4221 -4141 -4086 -4031 -3976 -3921 -3866 -3811 -3756 -3701 -3646 -3591 -3536 -3481 -3426 -3371 -3316 -3261 -3206 -3151 -3096 -2870 -2800 -2730 -2660 -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1820 -1750 -1680 -1610 -1540 -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -910 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 duty0 duty1 vss vdd vdd vdd vci vci vss vss vss vout vout c4+ c4+ c3+ c3+ c1- c1- c1+ c1+ c2+ c2+ c2- c2- vdd vext ref vss v1 v1 v2 v2 v3 v3 v4 v4 v0 v0 vr vr vss vss vdd ms cls vss c68 ps vdd -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 2030 2100 2170 2240 2310 2380 2450 2520 2590 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 hpmb vss intrs vdd com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 coms 2660 2730 2800 2870 3096 3151 3206 3261 3316 3371 3426 3481 3536 3591 3646 3701 3756 3811 3866 3921 3976 4031 4086 4141 4221 4345 4345 4345 4345 4345 4345 4345 4345 4345 4345 4345 4221 4141 4086 4031 3976 3921 3866 3811 3756 3701 3646 3591 3536 3481 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -865 - 865 - 865 - 865 - 865 - 865 -865 -865 -865 -865 -865 -865 -865 -865 -865 -750 -600 -450 -300 -150 0 150 300 450 600 750 865 865 865 865 865 865 865 865 865 865 865 865 865 865
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 6 table 2 . p ad center coordinates (continued) [unit: m m] pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 3406 3354 3302 3250 3198 3146 3094 3042 2990 2938 2886 2834 2782 2730 2678 2626 2574 2522 2470 2418 2366 2314 2262 2210 2158 2106 2054 2002 1950 1898 1846 1794 1742 1690 1638 1586 1534 1482 1430 1378 1326 1274 1222 1170 1118 1066 1014 962 910 858 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 806 754 702 650 598 546 494 442 390 338 286 234 182 130 78 26 -26 -78 -130 -182 -234 -286 -338 -390 -442 -494 -546 -598 -650 -702 -754 -806 -858 -910 -962 -1014 -1066 -1118 -1170 -1222 -1274 -1326 -1378 -1430 -1482 -1534 ? 1586 -1638 -1690 -1742 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 seg129 seg130 seg131 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 dummy dummy dummy dummy dummy -1794 -1846 -1898 -1950 -2002 -2054 -2106 -2158 -2210 -2262 2314 -2366 -2418 -2470 -2522 -2574 -2626 -2678 -2730 -2782 -2834 -2886 -2938 -2990 -3042 -3094 -3146 -3198 -3250 -3302 -3354 -3406 -3481 -3536 -3591 -3646 -3701 -3756 -3811 -3866 -3921 -3976 -4031 -4086 -4141 -4221 -4345 -4345 -4345 -4345 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 865 750 600 450 300
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 7 table 2. p ad center coordinates (continued) [unit: m m] pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 301 302 303 304 305 306 307 dummy dummy dummy dummy dummy dummy dummy -4345 - 4345 - 4345 - 4345 - 4345 - 4345 -4345 150 0 - 150 - 300 - 450 - 600 -750
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 8 pin description power supply table 3. power supply pins description name i/o description vdd supply power supply v ss supply ground lcd driver supply voltages the voltage determined by lcd pixel is impedance - converted by an operational amplifier for application. voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/ 9 bias ( 8/9 ) x v0 ( 7/9 ) x v0 ( 2/9 ) x v0 ( 1/9 ) x v0 1/ 8 bias (7 / 8) x v0 ( 6/ 8) x v0 ( 2/8 ) x v0 ( 1/8 ) x v0 1/ 7 bias (6 / 7) x v0 (5/ 7 ) x v0 ( 2/7 ) x v0 ( 1/7 ) x v0 1/ 6 bias (5 / 6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/6 ) x v0 v0 v1 v2 v3 v4 i/o 1/ 5 bias (4 / 5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/5 ) x v0 lcd driver supply table 4. lcd driver supply pins description name i/o description c1- o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2- o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 positive connection pin for voltage converter c 3 + o capacitor 3 positive connection pin for voltage converter c4+ o capacitor 4 positive connection pin for voltage converter vout i/o voltage converter input/output pin connect this pin to v ss through capacitor. vr i v0 voltage adjustment pin it is valid only when internal voltage regulator resistors are not used (intrs = " l ") . vci i this is the reference voltage for the voltage converter circuit for the lcd driving. whether internal voltage converter use or not use, this pin should be fixed. the voltage should have the following range: 2.4v vci 3.6v vext i this is the external-input reference voltage (v ref ) for the internal voltage regulator. it is valid only when external v ref is used ( ref = " l ") . when using internal v ref, this pin is open ref i select the external v ref voltage via vext pin - ref = " l ": u sing the external v ref - ref = " h ": u sing the internal v ref
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 9 system control table 5. system control pins description name i/o description master / slave mode select input master makes some signals for display, and slave gets them. this is for display synchronization. - ms = "h": master mode - ms = "l": slave mode the following table depends on the ms status. ms cls osc c ircuit power s upply c ircuit cl m fr disp h enabled enabled output output output output h l disabled enabled input output output output l - disabled disabled input input output input ms i cl s i built-in oscillator circuit enable / disable select pin - cls = ? h ? : e nable - cls = ? l ? : d isable ( e xternal display clock input to cl pin) cl i/o display clock input / output pin when the S6B0723 is used in master/slave mode (multi-chip), the cl pin s must be connected each other. m i/o lcd ac s ignal input / output pin when the S6B0723 is used in master/slave mode (multi-chip), the m pin s must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput frs o static driver segment output pin this pin is used together with the fr pin. fr o static driver common output pin this pin is used together with the frs pin. disp i/o lcd display blanking control input / output when S6B0723 is used in master/slave mode (multi-chip), the disp pins must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput intrs i internal resistor select pin this pin selects the resistors for adjusting v0 voltage level and is valid only in master operation . - intrs = "h": use the internal resistors . - intrs = "l": use the external resistors . v0 voltage is controlled by vr pin and external resistive divider.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 10 table 5. system control pins description (continued) name i/o description the lcd driver duty ratio depends on the following table . duty1 duty0 duty r atio l l 1/33 l h 1/49 h l 1/55 h h 1/65 duty0 duty1 i hpm b i power control pin of the power supply circuit s for lcd driver. - hpm b = " h ": normal mode - hpm b = " l ": high power mode this pin is valid only in master operation.
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 11 microprocessor interface table 6. microprocessor i nterface pins description name i/o description resetb i reset input pin when resetb is " l ", initialization is executed. parallel / serial data input select input ps interface mode chip s elect data / instruction data read / write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rdb rw_wrb - l serial cs1b, cs2 rs sid (db7) write only sclk (db6) ps i *note: in serial mode , it is impossible to read data from the on-chip ram. and db0 to db5 are high impedance and e_rdb and rw_wrb must be fixed to either "h" or " l ". c68 i microprocessor interface select input pin in parallel mode - c68 = "h": 6800-series mpu interface - c68 = "l": 8080-series mpu interface cs1b cs2 i chip select input pins data/instruction i/o is enabled only when cs1b is " l " and cs2 is "h". when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wrb description h 6800-series rw read / write control input pin - rw = "h": read - rw = " l ": write l 8080-series /wr b write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr b signal. rw_wrb i
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 12 table 6. microprocessor interface pins description (continued) name i/o description read / write execution control pin c68 mpu type e_rdb description h 6800-series e read/write control input pin - rw = "h": when e is "h", db0 to db7 are in an output status. - rw = "l": the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd b read enable clock input pin when /rd b is "l", db0 to db7 are in an output status. e_rdb i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance. test1 to test4 i/o these are pins for ic chip testing they are set to open. note: dummy ? these pins should be opened (floated).
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 13 lcd driver outputs table 7. lcd driver output pins description name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data fr normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg 0 to seg 131 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data fr common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com 0 to com 63 o coms o common output for the icons the output signals of two pins are same. when not used, these pins should be left o pen. in multi-chip (master / slave) mode, all coms pins on both master and slave units are the same signal.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 14 functional description microprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the S6B0723 can interface with an mpu only when cs1b is "l" and cs2 is "h". when these pins are set to any other combination, rs, e_rdb, and rw_wrb inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface S6B0723 has three types of interface with an mpu, which are one serial and two parallel interface s . this parallel or serial interface is determined by ps pin as shown in t able 8 . table 8 . parallel / serial interface mode ps type cs1b cs2 c68 interface mode h 6800-series mpu mode h parallel cs1b cs2 l 8080-series mpu mode l serial cs1b cs2 * serial-mode * : don't care parallel interface (ps = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rdb and rw_wrb as shown in table 10 . table 9 . microprocessor selection for parallel interface c68 cs1b cs2 rs e_rdb rw_wrb db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800-series l cs1b cs2 rs /rd b /wr b db0 to db7 8080-series table 10 . parallel data transfer common 6800-series 8080-series rs e_rdb (e) rw_wrb (rw) e_rdb (/rd b ) rw_wrb (/wr b ) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 15 serial interface (ps = "l") when the S6B0723 is active, serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. s erial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. s erial data input is display data when rs is high and control data when rs is low. since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . serial interface timing busy flag the b usy f lag indicates whether the S6B0723 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 16 data transfer the S6B0723 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 4 . and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure5 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. rs /wr b db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr b bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 4 . write timing
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 17 rs /wr b /rd b db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr b /rd b bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 5 . read timing
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 18 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 65 -row by 1 32 -column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com 0 - - com 1 - - com 2 - - com 3 - - com 4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 display data ram lcd display figure 6 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in figure 8 . it incorporates 4-bit p age a ddress register changed by only the "set page" instruction. page address 8 (db3 is "h", but db2, db1 and db0 are "l") is a special ram area for the icons and display data db0 is only valid. when page address is above 8, it is impossible to access to on-chip ram. line address circuit this circuit assigns ddram a l ine ad dress corresponding to the first line (com 0 ) of the display. therefore, by setting l ine a ddress repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 8 . it incorporates 6 -bit line address register changed by only the i nitial d isplay l ine instruction and 6 -bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine a ddress for transferring the 1 32 -bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 19 column address circuit column a ddress circuit has a n 8 -bit preset counter that provides column address to the display data ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 8 -bit [y 7 :y0] is updated. and, since this address is increased by 1 each a r ead or w rite data instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non-existing address above 84 h. it is unlocked if a column address is set again by set column address msb / lsb instruction. and t he c olumn a ddress counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the c olumn a ddress and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc s elect instruction. refer to the following figure 7. seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 128 seg 129 seg 130 seg 131 column address [y 7 :y0] 00h 01h 02h 03h ... ... 8 0h 8 1h 8 2h 8 3h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 7 . the relationship b etween t he column address a nd t he segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 20 start 1/55 duty page0 page2 page1 page4 page3 page6 page5 page7 page8 line address com output page address db3 db0 db1 db2 data - - - - - - - - - - seg131 seg130 seg1 seg0 seg129 seg128 seg127 seg126 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 28h 27h 26h 25h 24h 23h 22h 21h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 38h 37h 36h 35h 34h 33h 32h 31h 39h 3ah 3bh 3ch 3dh 3eh 3fh coms 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1/49 duty 1/33 duty com0 83 81 7f 80 7e 00 - 02 04 03 05 05 04 03 01 02 00 7e 7f 80 82 81 83 01 82 when the initial display line address is 1c[hex] com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com39 com38 com37 com36 com35 com33 com34 com32 com31 com40 com49 com48 com47 com46 com45 com43 com44 com42 com41 com50 com59 com58 com57 com56 com55 com53 com54 com52 com51 com60 com63 com62 com61 figure 8 . display data ram map
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 21 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. the oscillator circuit is only enabled when ms = ? h ? and cls = ? h ". when on-chip oscillator is not used, cls pin must be "l" condition. in this time, external clock must be input from cl pin . display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of on-chip ram is generated in synchronization with the display clock (cl) and the 132-bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display data ram from the microprocessor. the lcd ac signal, m is generated from the display clock. 2-frame ac driver waveform s with internal timing signal are shown in figure 9 . in a multi ple chip configuration , the slave chip requires the m , cl and disp signals from the master. table 11 shows the m, sync , cl, and disp status. table 11 . master and slave timing signal status operation mode oscillator m cl disp on (internal clock used) output output output master off (external clock used) output input output slave - input input input
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 22 com0 v0 v1 v2 v3 v4 v ss com1 v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss segn 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl fr figure 9 . 2-frame ac driving waveform ( d uty ratio = 1/ 6 5)
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 23 common output control circuit this circuit controls the relationship between the number of common output and specified duty ratio. shl s elect i nstruction specifies the scanning direction of the common output pins . table 12. the relationship between duty ratio and common output common o utput p ins duty shl com [0:15] com [16:23] com [24:26] com [27:36] com [37:39] com [40:47] com [48:63] coms 0 com[0:15] *nc com[16:31] 1/33 1 com[31:16] *nc com[15:0] coms 0 com[0:23] *nc com[24:47] 1/49 1 com[47:24] *nc com[23:0] coms 0 com[0:26] *nc com[27:53 ] 1/55 1 com[53:27] *nc com[26:0] coms 0 com[0:63] 1/65 1 com[63:0] coms *nc: no connection
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 24 lcd driver circuit s this driver circuit is configured by 66-c hannel (including 2 coms channels) common driver and 1 32 -channel segment driver. this lcd panel driver voltage depends on the combination of display data and fr signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 f r v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 10 . segment and common timing
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 25 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by power control instruction. for details, refers to "instruction description". table 13 shows the referenced combinations in using p ower s upply circuits. table 13 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 26 voltage converter circuits these circuits boost up the electric potential between vci and v ss to 2, 3, 4, or 5 times toward positive side and boosted voltage is outputted from vout pin. [c1 = 1.0 to 4.7 m f] vout = 2 vci v ss vci c1 + - - + - + c1 c1 c1 + - - + c1 vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vout = 3 vci v ss vci vci vdd vdd vci figure 11 . two times boosting circuit figure 12 . three times boosting circuit c1 c1 c1 + - - + + - + c1 + c1 c1 + - - + - + c1 + c1 c1 - vout = 4 vci v ss vci vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vout = 5 vci vci v ss vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vci vci vdd vdd figure 13 . four times boosting circuit figure 14 . five times boosting circuit * the vci voltage range must be set so that the vout voltage does not exceed the absolute maximum rated value
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 27 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational- amplifier circuits shown in figure 15 , it is necessary to be applied internally or externally. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 14-1 . rb v0 = ( 1 + ???? ) x v ev [v] ------ ( eq. 1) ra (63 - a ) v ev = ( 1 - ?????? ) x v ref [v] ------ ( eq. 2) 162 table 14-1. v ref voltage at ta = 25 c ref temp. coefficient v ref [v] h -0.05% / c 2.1 l external i nput vext table 14-2. electronic contrast control register (64 steps) s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) v0 contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efault) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 28 v ev gnd ra rb v ss vr v0 vout + - figure 15 . internal v oltage r egulator c ircuit
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 29 in case of using internal resistors, ra and rb (intrs = "h") when intrs pin is "h", resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 15 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 the following figure shows v0 voltage measured by adjusting internal regulator re s ist o r ratio ( rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 electronic volume level v0 [v] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) figure 16 . electronic volume level
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 30 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is "l", it is necessary to connect external regulator resistor ra between vr and v ss , and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. m aximum current flowing ra, rb = 1 ua from eq. 1 rb 10 = ( 1 + ??? ) x v ev [v] ------ ( eq. 3) ra from eq. 2 (63 - 32) v ev = ( 1 - ?????? ) x 2.1 @ 1. 698 [v] ------ ( eq. 4) 162 from requirement 3. 10 ?????? = 1 [ ua] ------ ( eq. 5) ra + rb from equations eq. 3, 4 and 5 ra @ 1.69 [m w ] rb @ 8. 31 [m w ] the following table shows the range of v0 depending on the above requirements. table 16. v0 d epending on electronic volume l evel electronic volume level 0 ....... 32 ....... 63 v0 7 . 57 ....... 10.00 ....... 1 2 . 43
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 31 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. the following table shows the relationship between v1 to v4 level and each duty ratio. table 17. the relationship between v1 to v4 l evel and duty ratio duty r atio duty1 duty0 lcd bias v1 v2 v3 v4 1/5 (4/5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/ 5) x v0 1/33 l l 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/49 l h 1/8 (7/8) x v0 (6 / 8) x v0 ( 2/ 8) x v0 ( 1/ 8) x v0 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/55 h l 1/8 (7/8) x v0 (6 / 8) x v0 ( 2/ 8) x v0 ( 1/ 8) x v0 1/ 7 (6/7) x v0 (5 / 7) x v0 ( 2/ 7) x v0 ( 1/ 7) x v0 1/65 h h 1/9 (8/9) x v0 (7 / 9) x v0 ( 2/ 9) x v0 ( 1/ 9) x v0 high p ower m ode the power supply circuit equipped in the S6B0723 for lcd drive has very low power consumption (in normal mode: hpmb = ? h ? ). if use for lcd panels with large loads, this low-power power supply may cause display quality to degrade. when this occurs, setting the hpmb pin to ? l ? (high power mode) can improve the quality of the display. moreover, if the quality of display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally ( vout or v0 or v1 / v2 / v3 / v4).
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 32 reference circuit examples ms intrs v ss c2 - + c2 - + c2 - + c2 - + c2 - + v dd ms intrs v ss c1 ra rb v ss v dd vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vci v ss vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 c1 c1 c1 c1 c1 when using internal regulator resistors when not using internal regulator resistors c1 c1 figure 17. when using a ll internal lcd power circuits (vci = vdd, 4- t ime v/c: o n , v/r: on , v/f: on ) when using internal regulator resistors when not using internal regulator resistors v dd ms intrs v ss ra rb v ss v dd ms intrs v ss external power supply external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vci vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vci vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 figure 18. when using s ome internal lcd power circuits (vci = vdd, v/c: o ff , v/r: o n , v/f: o n )
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 33 ms intrs v ss c2 - + c2 - + c2 - + c2 - + c2 - + v dd vci vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 external power supply figure 19. when using s ome internal lcd power circuits (vci = vdd, v/c: o ff , v/r: o ff , v/f: o n ) v dd ms intrs v ss external power supply vci vout c4+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 value of external capacitance item value unit c1 1.0 to 4.7 c2 0.47 to 1.0 m f figure 20. when n ot using a ny internal lcd power supply circuits (vci = vdd, v/c: o ff, v/r: o ff , v/f: o ff ) * c1 and c2 are determined by the size of the lcd being driven. select a value that will stabilize the liquid crystal drive voltage.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 34 reset circuit setting resetb to " l " or reset instruction can initialize internal function. when resetb becomes " l " , following procedure is occurred. display on / off: off entire display on / off: off (normal) adc select: off (normal) reverse display on / off: off (normal) power control register (vc, vr, vf) = (0, 0, 0) serial interface internal register data clear lcd bias ratio: 1/ 9 (1/65 d uty), 1/8 (1/55 d uty), 1/8 (1/49 d uty), 1 /6 (1/33 d uty) on-chip oscillator off power save release r ead -m odify -write : off shl select: off (normal) static indicator mode: off static indicator register: (s1, s0) = (0, 0) d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 1 , 0, 0) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release when reset instruction is issued, following procedure is occurred. r ead -m odify- write : off static indicator mode: off static indicator register: (s1, s0) = (0, 0) shl select: 0 d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = ( 1 , 0, 0) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) test mode release while resetb is "l" or reset instruction is executed, no instruction except read status c ould be accepted. reset status appears at db4. after db4 becomes "l", any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 35 instruction description table 18 . instruction table : don't care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description display on / off 0 0 1 0 1 0 1 1 1 d on turn on / off lcd panel when d on = 0: display off when d on = 1: display on initial display line 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 specify ddram line for com0 set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y7 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb read status 0 1 busy adc on /off res etb 0 0 0 0 read the internal status write display data 1 0 write data write data into ddram read display data 1 1 read data read data from ddram adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc = 0 : normal direction (seg0 ? seg131) when a dc = 1 : reverse direction (seg131 ? seg0) reverse display on / off 0 0 1 0 1 0 0 1 1 rev select normal / reverse display when rev = 0 : normal display when rev = 1 : reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal/ entire display on when eon = 0 : normal display. when eon = 1 : entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl = 0 : normal direction (com0 ? com63) when shl = 1: reverse direction (com63 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 set r eference v oltage m ode set r eference v oltage r egister 0 0 s v5 s v4 s v3 s v2 s v1 s v0 set r eference v oltage r egister set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode set static indicator register 0 0 s1 s0 set static indicator register power s ave - - - - - - - - - - compound instruction of display off and entire display on
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 36 table 18 . instruction table (continued) : don't care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description nop 0 0 1 1 1 0 0 0 1 1 non-operation command test i i struction_1 0 0 1 1 1 1 don ? t use this instruction test i nstruction_2 0 0 1 0 0 1 don ? t use this instruction
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 37 display on / off turns the d isplay on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off initial display line sets the line address of display ram to determine the i nitial d isplay l ine . the ram display data is displayed at the top row (com 0 when shl = l, com63 when shl = h ) of lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 s et page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age a ddress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the page address doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 38 set column address sets the c olumn a ddress of display ram from the microprocessor into the c olumn a ddress register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, co lumn a ddresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y7 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 read status indicates the internal status of the S6B0723 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on / off res etb 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg 131 ? seg 0 ), 1: normal direction (seg 0 ? seg 131 ) on / off indicates display on / off status. 0: display on, 1: display off res etb indicates the initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 39 write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 21 . sequence for writing display data figure 22 . sequence for reading display data read display data 8-bit data from display data ram specified by the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data adc select ( segment driver direction select) changes the relationship between ram column address and segment driver. the direction of segment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 131 ) adc = 1: reverse direction (seg 131 ? seg 0 )
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 40 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = "1" ram bit data = "0" 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the reverse display on/off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal di splay eon = 1: e ntire d isplay o n select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias lcd bias d uty r atio d uty 1 d uty0 b ias = 0 b ias = 1 1/33 0 0 1/ 6 1/5 1/49 0 1 1/ 8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/ 9 1/7 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 41 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify-read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no yes change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 23 . sequence for cursor display reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 42 shl select ( common output mode select ) com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? com 63 ) shl = 1: reverse direction (com 63 ? com 0 ) power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 (1 + rb / ra) ratio 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 (default) 1 0 1 5.5 1 1 0 6.0 1 1 1 6.4
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 43 r eference voltage select consists of 2-byte instruction. the 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st instruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 sv5 s v4 s v3 s v2 s v1 s v0 s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) v0 contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 0 0 0 0 0 32 ( d efault) : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 minimum : : : : : maximum low : : : : : high 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 24 . sequence for setting the r eference v oltage
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 44 set static indicator state consists of two bytes instruction. the first byte instruction ( s et static indicator mode) enables the second byte instruction ( s et static indicator register) to be valid. the first byte sets the static indicator on / off . when it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this s tatic i ndicator state is released after setting the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1: static indicator on the 2 nd instruction: set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 1 second blinking) 1 0 on (about 0.5 second blinking) 1 1 on (always on) nop non operation i nstruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 t est instruction ( test instruction _1 & test instruction_ 2) these are the instruction for ic chip testing. please do not use it. if the test instruction is used by accident, it can be cleared by applying ? 0 ? signal to the resetb input pin or the reset instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 0 0 1 0 0 1
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 45 p ower save ( compound instruction ) if th e e ntire d isplay on / off instruction is issued during the display off state, S6B0723 enters the power save status to reduce the power consumption to the static power consumption value. according to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. when static indicator mode is on, standby mode is issued. when off, sleep mode is issued. power s ave mode is released by the e ntire d isplay off instruction. sleep mode [oscillator c ircuit: o ff] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <2ua] power save off (compound instruction) [entire display o ff ] [static indicator on] 2 b ytes c ommand power save (compound instruction) [display off] [entire display on] static indicator off static indicator on standby mode [oscillator c ircuit: on] [lcd power s upply c ircuit: off] [all com / seg o utputs: vss] [consumption c urrent: <10ua] power save off [entire display o ff ] release sleep mode release standby mode figure 25. power save (compound instruction) - sleep mode this stops all operations in the lcd display system, and as long as there are no access from the mpu, the consumption current is reduced to a value near the static current. the internal modes during sleep mode are as follows: a. the oscillator circuit and the lcd power supply circuit are halted. b. all liquid crystal drive circuits are halted, and the segment in common drive outputs output a v ss level. - standby mode the duty lcd display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. the internal modes are in the following states during standby mode. a. the lcd power supply circuits are halted. the oscillator circuit continues to operate. b. the duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs a v ss level. the static drive system does not operate. when a reset command is performed while in standby mode, the system enters sleep mode.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 46 r eferential instruction setup flow (1) end of initialization waiting for stabilizing the lcd power levels user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins user lcd p ower setup by internal instructions [voltage converter on] user lcd p ower setup by internal instructions [voltage regulator on] user lcd p ower setup by internal instructions [voltage follower on] user lcd p ower setup by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for 3 1ms waiting for 3 1ms figure 26 . initializing with the b uilt-in p ower s upply c ircuits
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 47 r eferential instruction setup flow (2) user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of iitialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins set power save release power save user lcd p ower setup by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for stabilizing the lcd power levels end of initialization figure 27 . initializing without the b uilt-in p ower s upply c ircuits
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 48 r eferential instruction setup flow (3) end of initialization write display on / off by instruction [display o n /off] display data ram addressing by instruction [initial display line] [set page address] [set column address] end of data display turn display on / off by instruction [display o n / off ] figure 28 . data d isplaying
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 49 r eferential instruction setup flow (4) turn display on /off by instruction [display o ff ] optional status power off (v dd - v ss ) user lcd power setup by internal instructions [voltage follower o ff ] user lcd power setup by internal instructions [voltage regulator o ff ] user lcd power setup by internal instructions [voltage converter o ff ] waiting for 3 50ms waiting for 3 1ms waiting for 3 1ms figure 29 . power o ff
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 50 specifications absolute maximum ratings table 19. absolute maximum ratings parameter symbol rating unit v dd - 0.3 to + 7.0 v supply voltage range v lcd - 0.3 to + 17 .0 v input voltage range v in - 0.3 to v dd + 0.3 v operating temperature range t opr - 40 to +85 c storage temperature range t str - 55 to +125 c notes: 1. vdd and vlcd are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. ( vlcd = v0 ? vss) 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 51 dc characteristics table 20. dc characteristics (v ss = 0v, v dd = 2.4 to 3.6v, ta = -40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v vdd *1 operating voltage (2) v0 4.5 - 1 5 .0 v v0 *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = -0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a * 5 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a * 6 lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn * 7 internal f osc 32.7 43.6 54.5 oscillator frequency external f cl ta = 25 c duty ratio = 1/65 4.09 5.45 6.81 khz cl *8 2 2.4 - 3.6 3 2.4 - 3.6 4 2.4 - 3.6 voltage converter input voltage vci 5 2.4 - 3.2 v vci voltage converter output voltage vout 2 / 3 / 4 / 5 voltage conversion (no-load ) 95 99 - % vout voltage regulator operating voltage vout 6 .0 - 1 6 .0 v vout voltage follower operating voltage v0 4. 5 - 1 5 .0 v v0 * 9 reference voltage v ref ta = 25 c - 0.05%/ c 2.04 2.1 2.16 v * 10
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 52 dynamic current consumption (1) when the b uilt-in power c ircuit is off (at o perate m ode) ( ta = 25 c) item symbol condition min. typ. max. unit pin used dynamic current consumption (1) i dd1 v dd = 3.0v v0 ? v ss = 11.0v 1/65 d uty ratio display p attern off - 15 23 m a *11 dynamic current consumption (2) when t he b uilt-in p ower c ircuit is on (at o perate m ode) ( ta = 25 c ) item symbol condition min. typ. max. unit pin used v dd = 3.0 v, (vci = v dd , 4 times boosting ) v0 ? v ss = 11.0 v, 1/65 duty ratio, display pattern off, normal power mode - 40 60 m a *1 2 dynamic current consumption (2) i dd2 v dd = 3.0 v, (vci = v dd , 4 times boosting ) v0 ? v ss = 11.0 v, 1/65 duty ratio, display pattern checker, normal power mode - 150 200 m a *1 2 current consumption during power save m ode ( ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during s leep - - 2.0 m a standby mode current i dd s 2 during s tandby - - 10.0 m a
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 53 table 21 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f fr on-chip oscillator circuit is used f osc ???? 8 f osc ???? 2 8 65 1/ 65 on-chip oscillator circuit is not used external input ( f cl ) f osc ???? 2 65 on-chip oscillator circuit is used f osc ???? 9 f osc ???? 2 9 55 1/55 on-chip oscillator circuit is not used external input ( f cl ) f osc ???? 2 55 on-chip oscillator circuit is used f osc ???? 10 f osc ???? 2 10 49 1/49 on-chip oscillator circuit is not used external input ( f cl ) f osc ???? 2 49 1/33 on-chip oscillator circuit is used f osc ???? 15 f osc ???? 2 15 33 on-chip oscillator circuit is not used external input ( f cl ) f osc ???? 2 33 ( f osc : oscillation frequency, f cl : display clock frequency, f fr : lcd ac signal frequency ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rdb, rw_wrb, resetb, ms, c68 , ps, intrs, hpm b , cls, cl, m, fr, disp pins . *4 . db0 to db7, m , fr, disp, cl pins. *5 . cs1b, cs2, rs, db[7:0], e_rdb, rw_wrb, resetb, ms, c68 , ps, intrs, hpm b , cls, cl, m, fr, disp pins. *6 . applies when the db[7:0], m, fr, disp, and cl pins are in high impedance. *7 . resistance value when 0.1[ ma] is applied during the on status of the output pin segn or comn. ron = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ ma] is applied in the on status.) *8 . see table 21 for the relationship between oscillation frequency and frame frequency. *9 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range *10 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *11,12. applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors (ra and rb) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 54 ac characteristics read / write characteristics (8080-series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw80(r) , t pw80(w) t cy80 t ah80 t as80 db 0 to db 7 (write) db 0 to db 7 (read) rd b , wr b cs1b (cs2=1) rs figure 30. read / write characteristics (8080-series mpu) (v dd = 2.4 to 3.6v, ta = -40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time rs t cy80 300 - - ns pulse width (wr b ) rw_wrb t pw80 (w) 60 - - ns pulse width (rd b ) e_rdb t pw80 (r) 60 - - ns data setup time data hold time t ds80 t dh80 40 15 - - ns read access time output disable time db7 to db0 t acc80 t od80 - 10 - 140 100 ns c l = 100 pf
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 55 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw68(r) , t pw68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e cs1b (cs2=1) rs db 0 to db 7 (read) figure 31. read / write characteristics (6800-series microprocessor) (v dd = 2.4 to 3.6 v, ta = -40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as68 t ah68 0 0 - - ns system cycle time rs t cy68 300 - - ns data setup time data hold time t ds68 t dh68 40 15 - - ns access time output disable time db7 to db0 t acc68 t od68 - 10 - 140 100 ns c l = 100 pf enable pulse width read write e_rdb t pw68(r) t pw68(w) 120 60 - - -
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 56 serial interface characteristics db7 (sid) db6 (sclk) rs cs1b (cs2 = 1) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 32. serial interface characteristics (v dd = 2.4 to 3.6 v, ta = -40 to +85 c) item signal symbol min. typ . max. unit remark serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 250 100 100 - - - - - - ns address setup time address hold time rs t ass t ahs 150 150 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 100 100 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 150 150 - - - - ns
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 57 reset input timing resetb t rw internal status t r during reset reset complete figure 33. reset input timing (v dd = 2.4 to 3.6 v, ta = -40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 1.0 - - m s reset time - t r - - 1.0 m s display control output timing t dfr cl (out) fr figure 34. display control output timing (v dd = 2.4 to 3.6 v, ta = -40 to +85 c) item signal symbol min. typ . max. unit remark fr d elay t ime fr t dfr - 20 80 ns c l = 50 pf
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 58 reference applications microprocessor interface in case of interfacing with 6800-series (ps = "h", c68 = "h") db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 23 figure 35. i nterfacing with 6800-series (ps = "h", c68 = "h") in case of interfacing with 8080-series (ps = "h", c68 = "l") db0 to db7 resetb v dd v ss wr b rd b rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd b rw_wr b db0 to db7 resetb c68 ps s 6b 07 23 figure 36. i nterfacing with 8080-series (ps = "h", c68 = "l") in case of serial interface (ps = "l", c68 = "h or l") open resetb v ss v dd or v ss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s 6b 07 23 figure 37. s erial i nterface (ps = "l", c68 = "h or l")
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 59 connections between S6B0723 and lcd panel single chip structure (1/ 6 5 duty configurations) com 32 : com 6 3 coms coms com 0 : com 3 1 seg 0 ........... seg13 1 s 6b 07 2 3 (bottom view) ? a x a ? a x a 64 132 pixels com s com 0 : com 31 com3 2 : com6 3 coms seg13 1 ........... seg 0 s 6b 07 2 3 (top view) ? a x a ? a x a 64 132 pixels figure 38 . shl = 1, adc = 0 figure 39 . shl = 1 , adc = 1 coms com 6 3 : com 32 com 3 1 : com 0 coms seg 0 ........... seg13 1 s 6b 07 2 3 (top view) coms com 6 3 : com 32 com 3 1 : com 0 coms seg13 1 ............ seg 0 s 6b 07 2 3 (bottom view) ? a x a ? a x a 64 132 pixels ? a x a ? a x a 64 132 pixels figure 40 . shl = 0 , adc = 0 figure 41 . shl = 0, adc = 1
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 60 single chip structure (1/ 55 duty configurations) com 37 : com 6 3 coms coms com 0 : com 26 seg 0 ........... seg13 1 s 6b 07 2 3 (bottom view) ? a x a ? a x a 5 4 132 pixels com s com 0 : com 26 com 37 : com 63 coms seg13 1 ........... seg 0 s 6b 07 2 3 (top view) ? a x a ? a x a 5 4 132 pixels figure 42 . shl = 1, adc = 0 figure 43 . shl = 1, adc = 1 coms com 6 3 : com 37 com 26 : com 0 coms seg 0 ........... seg13 1 s 6b 07 2 3 (top view) coms com 6 3 : com 37 com 26 : com 0 coms seg13 1 ............ seg 0 s 6b 07 2 3 (bottom view) ? a x a ? a x a 5 4 132 pixels ? a x a ? a x a 5 4 132 pixels figure 44 . shl = 0 , adc = 0 figure 45 . shl = 0 , adc = 1
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 61 single chip structure (1/ 49 duty configurations) com 40 : com 6 3 coms coms com 0 : com 23 seg 0 ........... seg13 1 s 6b 07 2 3 (bottom view) ? a x a ? a x a 48 132 pixels com s com 0 : com 23 com 40 : com6 3 coms seg13 1 ........... seg 0 s 6b 07 2 3 (top view) ? a x a ? a x a 4 8 132 pixels figure 46 . shl = 1 , adc = 0 figure 47 . shl = 1 , adc = 1 coms com 6 3 : com 40 com 23 : com 0 coms seg 0 ........... seg13 1 s 6b 07 2 3 (top view) coms com 6 3 : com 40 com 23 : com 0 coms seg13 1 ............ seg 0 s 6b 07 2 3 (bottom view) ? a x a ? a x a 48 132 pixels ? a x a ? a x a 48 132 pixels figure 48 . shl = 0 , adc = 0 figure 49 . shl = 0 , adc = 1
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 62 single chip structure (1/ 33 duty configurations) com 48 : com 6 3 coms coms com 0 : com 15 seg 0 ........... seg13 1 s 6b 07 2 3 (bottom view) ? a x a ? a x a 32 132 pixels com s com 0 : com 15 com 48 : com6 3 coms seg13 1 ........... seg 0 s 6b 07 2 3 (top view) ? a x a ? a x a 32 132 pixels figure 50 . shl = 1, adc = 0 figure 51 . shl = 1, adc = 1 coms com 6 3 : com 48 com 15 : com 0 coms seg 0 ........... seg13 1 s 6b 07 2 3 (top view) coms com 6 3 : com 48 com 15 : com 0 coms seg13 1 ............ seg 0 s 6b 07 2 3 (bottom view) ? a x a ? a x a 32 132 pixels ? a x a ? a x a 32 132 pixels figure 52 . shl = 0, adc = 0 figure 53 . shl = 0, adc = 1
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 63 mu l ti pl e c hip structure - 65com (64com + 1coms) 264seg (132seg 2) ? a x a ? a x a 64 264 pixels coms com 0 : com 3 1 com 32 : com 6 3 coms seg13 1 ............... seg 0 s 6b 07 2 3 ( top view) (master) coms com 0 : com 31 com 32 : com63 coms seg13 1 ............... seg 0 s 6b 07 2 3 ( top view) (slave) figure 54 . shl = 1, adc = 1 connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 coms com 63 : com 32 com 3 1 : com 0 coms seg 0 ................... seg13 1 s 6b 07 2 3 (top view) (master) coms com 6 3 : com 32 com 3 1 : com 0 coms seg 0 ................... seg13 1 s 6b 07 2 3 (top view) (slave) ? a x a ? a x a 64 264 pixels figure 55 . shl = 0, adc = 0 connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 64 - 130com (128com + 2coms) 132seg coms com0 : com31 com32 : com63 coms seg1 31 ................... seg0 s 6b 0723 (top view) (slave) com s com 63 : com 32 com 31 : com 0 com s seg0 ................... seg 131 s 6b 0723 (top view) (master) ? a x a ? a x a 128 132 pixels figure 56. 130com (128com + 2coms) 132seg connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 common/segment output direction select - master c hip: shl = 0, adc = 0 - slave c hip: shl = 1, adc = 1
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 65 S6B0723 application circuit (6800 / 8080 / serial) S6B0723 application circuit for 6800- s eries n package type: tcp n device mode: master mode, internal osc, normal mode, 4 t imes b oost -u p, internal rb / ra frs fr test1 test2 test3 m cl disp test4 vss cs1b cs2 vdd resetb rs vss rw_wrb e_rdb vdd db0 db1 db2 db3 db4 db5 db6 db7 vss vdd duty0 duty1 vss vdd [3] vci [2] vss [3] vout [2] c4+ [2] c3+ [2] c1- [2] c1+ [2] c2+ [2] c2- [2] vdd vext ref vss v1 [2] v2 [2] v3 [2] v4 [2] v0 [2] vr [2] vss [2] vdd ms cls vss c68 ps vdd hpmb vss intrs vdd S6B0723 mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu v dd v ss tcp outside figure 57. S6B0723 application circuit for 68- s eries
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 66 S6B0723 application circuit for 8080- s eries n package type: tcp n device mode: master mode, internal osc, normal mode, 4 t imes b oost - up, internal rb / ra frs fr test1 test2 test3 m cl disp test4 vss cs1b cs2 vdd resetb rs vss rw_wrb e_rdb vdd db0 db1 db2 db3 db4 db5 db6 db7 vss vdd duty0 duty1 vss vdd [3] vci [2] vss [3] vout [2] c4+ [2] c3+ [2] c1- [2] c1+ [2] c2+ [2] c2- [2] vdd vext ref vss v1 [2] v2 [2] v3 [2] v4 [2] v0 [2] vr [2] vss [2] vdd ms cls vss c68 ps vdd hpmb vss intrs vdd S6B0723 mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu mpu v dd v ss tcp outside figure 58. S6B0723 application circuit for 80- s eries
S6B0723 preliminary spec. ver. 0.9 6 5 com / 1 32 seg driver & controller for stn lcd 67 S6B0723 application circuit for serial n package type: tcp n device mode: master mode, internal osc, normal mode, 4 t ime s b oost - up, internal rb / ra frs fr test1 test2 test3 m cl disp test4 vss cs1b cs2 vdd resetb rs vss rw_wrb e_rdb vdd db0 db1 db2 db3 db4 db5 db6 (scl) db7 (si) vss vdd duty0 duty1 vss vdd [3] vci [2] vss [3] vout [2] c4+ [2] c3+ [2] c1- [2] c1+ [2] c2+ [2] c2- [2] vdd vext ref vss v1 [2] v2 [2] v3 [2] v4 [2] v0 [2] vr [2] vss [2] vdd ms cls vss c68 ps vdd hpmb vss intrs vdd S6B0723 mpu mpu mpu mpu mpu v dd v ss tcp outside figure 59. S6B0723 application circuit for serial
132 seg / 65 com driver & controller for stn lcd p reliminary spec. ver. 0.9 S6B0723 68 tcp pin layout (sample) S6B0723 (top view) test1 (pad_ck) test2 (scl) test3 (sda) m cl disp test4 cs1b cs2 resetb rs rw_wr b e_rd b db0 db1 db2 db3 db4 db5 db6 db7 duty0 duty1 v dd vci v ss vout c4+ c3+ c1 - c1 + c2+ c2- vext ref v1 v2 v3 v4 v0 vr ms cls c68 ps hpm b intrs fr frs com s com63 com62 : : : com48 com47 com46 : : : com3 5 com 34 com33 com 32 seg131 seg130 seg129 seg128 : : : : seg66 seg65 seg64 seg63 : : : : seg3 seg2 seg1 seg0 coms com0 com1 : : : com15 com16 com17 : : : com2 8 com29 com30 com31 figure 60. tcp pin layout

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